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White Electronic Designs
8Mx32 SDRAM
FEATURES

53% Space Savings vs. Monolithic Solution Reduced System Inductance and Capacitance Pinout and Footprint Compatible to SSRAM 119 BGA 3.3V Operating Supply Voltage Fully Synchronous to Positive Clock Edge Clock Frequencies of 133MHZ, 125MHZ and 100MHZ Burst Operation
WED3DL328V
DESCRIPTION
The WED3DL328V is an 8Mx32 Synchronous DRAM configured as 4x2Mx32. The SDRAM BGA is constructed with two 8Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 119 lead, 14mm by 22mm, BGA. The WED3DL328V is an ideal SDRAM wide I/O memory solution for all high performance, computer applications which include Network Processors, DSPs and Functional ASICs. The WED3DL328V is available in clock speeds of 133MHZ, 125MHZ and 100MHZ. The range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The package and design provides performance enhancements via a 50% reduction in capacitance vs. two monolithic devices. The design includes internal ground and power planes which reduces inductance on the ground and power pins allowing for improved decoupling and a reduction in system noise.

Sequential or Interleave Burst Length = Programmable 1, 2, 4, 8 or Full Page Burst Read and Write Multiple Burst Read and Single Write
Data Mask Control Per Byte Auto and Self Refresh Automatic and Controlled Precharge Commands Suspend Mode and Power Down Mode 119 Pin BGA, JEDEC MO-163
PIN CONFIGURATION (TOP VIEW)
1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQc DQc VCCQ DQc DQc VCCQ DQd DQd VCCQ DQd DQd NC NC VCCQ 1 2 NC NC NC NC DQc DQc DQc DQc VCC DQd DQd DQd DQd NC A6 NC NC 2 3 BA0 NC/A12* BA1 VSS VSS VSS DQMC VSS NC VSS DQMD VSS VSS VSS NC A5 NC 3 4 NC CAS# VCC NC CE# RAS# NC CKE VCC CK NC WE# A1 A0 VCC A4 NC 4 5 A10 A11 A9 VSS VSS VSS DQMB VSS NC VSS DQMA VSS VSS VSS NC A3 NC 5 6 A7 NC A8 NC DQb DQb DQb DQb VCC DQa DQa DQa DQa NC A2 NC NC 6 7 VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC NC VCCQ 7 A B C D E F G H J K L M N P R T U
PIN DESCRIPTION
A0 - A11 BA0-1 DQ CK CKE DQM RAS# CAS# CE# VCC VCCQ VSS Address Bus Bank Select Addresses Data Bus Clock Clock Enable Data Input/Output Mask Row Address Strobe Column Address Strobe Chip Enable Power Supply pins, 3.3V Data Bus Power Supply pins,3.3V Ground pins
*NOTE: Pin B3 is designated as NC/A12. This pin is used for future density upgrades as address pin A12.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FIG. 1 8MX32 SDRAM BLOCK DIAGRAM
ADDR0-11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11
WED3DL328V
BA0 BA1 DQMA DQMB CE# RAS# CAS# WE#
BA0 BA1
DQ0-7 DQ8-15
DQA DQB
LDQM# UDQM# CS# RAS# CAS# WE#
CK CKE
CK CKE
DQ0-31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11
BA0 BA1
DQ0-7 DQ8-15
DQC DQD
DQMC DQMD
LDQM# UDQM# CS# RAS# CAS# WE#
CK CKE
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INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK CKE CE# RAS#, CAS# WE# BA0,BA1 Type Input Input Input Input Input Signal Pulse Level Pulse Pulse Level Polarity Active High Active Low Active Low -- Function
WED3DL328V
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and DQM. When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. Data Input/Output are multiplexed on the same pins The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write Active High mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Power and ground for the input buffers and the core logic. Isolated power and ground for the output buffers to improve noise immunity.
A0-11, A10/AP
Input
Level
--
DQ DQM VCC, VSS VCCQ
Input/Output Input Supply Supply
Level Pulse
-- Mask
ABSOLUTE MAXIMUM RATINGS*
Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Symbol VCC/VCCQ VIN VOUT tOPR tSTG PD IOS Min -1.0 -1.0 -1.0 -0 -55 -- -- Max +4.6 +4.6 +4.6 +70 +125 1.5 50 Units V V V C C W mA
RECOMMENDED DC OPERATING CONDITIONS
(Voltage Referenced to: VSS = 0V, 0C TA 70C)
Symbol VCC/VCCQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -- -5 -5 Typ 3.3 3.0 -- -- -- -- -- 3.6 VCC +0.3 0.8 -- 0.4 5 5 Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage (IOH = -2mA) Output Low Voltage (IOL = 2mA) Input Leakage Voltage Output Leakage Voltage Max Unit V V V V V A A
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(TA = 25C, f = 1MHZ, VDD = 3.3V) Parameter Symbol Input Capacitance CI1 Input/Output Capacitance (DQ) COUT Max 4 5 Unit pF pF
CAPACITANCE
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OPERATING CURRENT CHARACTERISTICS (VCC = 3.6V)
Parameter Operating Current (One Bank Active) (1) Operating Current (Burst Mode) (1) Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode Precharge Standby Current in Power Down Mode Active Standby Current in Non-Power Down Mode (One Bank Active) Refresh Current (2) Self Refresh Current
NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms.
WED3DL328V
Symbol ICC1 ICC4 ICC2P ICC2PS ICC1N ICC1NS ICC3P ICC3PS ICC3N ICC3NS ICC5 ICC6
Conditions Burst Length = 1, tRC tRC(min), IOL = 0mA Page Burst, 4 banks active, tCCD = 2 clocks CKE VIL(max), tCC = 15ns CKE, CK VIL(max), tCC = , Inputs Stable CKE = VIH, tCC = 15ns Input Change one time every 30ns CKE VIH(min), tCC = No Input Change CKE VIL(max), tCC = 15ns CKE VIL(max), tCC = CKE = VIH, tCC = 15ns Input Change one time every 30ns CKE VIH(min), tCC = , No Input Change tRC tRC(min) CKE 0.2V
7 300 340 2 2 100 70 12 12 60 40 440 3
8 280 290 2 2 100 70 12 12 60 40 420 3
10 225 240 2 2 100 70 12 12 60 40 420 3
Units mA mA mA mA mA mA mA mA mA mA mA mA
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FIG. 2 MODE REGISTER DEFINITION
A11 A10 A9 A8
WED3DL328V
BURST DEFINITION
Burst Length 2 A1 0 0 1 1 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Starting Column Address A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 Order of Accesses Within a Burst Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... ...Cn - 1, Cn... Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported
A7
A6
A5 A4
A3 A2
A1 A0
Address Bus
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
BT
Burst Length
*Should program M11, M10 = "0, 0" to ensure compatibility with future devices.
M2 M1 M0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
Burst Length
M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page
M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved
0 1 0 1 0 1 0 1
4
M3
Burst Type Sequential Interleaved
8
0 1
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
Full Page (y)
n = A0-A11/9/8 (location 0-y)
M8
M7
M6-M0
Operating Mode Standard Operation All other states reserved
0 -
0 -
Defined -
M9 0 1
Write Burst Mode Programmed Burst Length Single Location Access
NOTES: 1. For full-page accesses: y = 2,048 (x4), y = 1,024 (x8), y = 512 (x16). 2. For a burst length of two, A1-A9, A11 (x4), A1-A9 (x8) or A1-A8 (x16) select the blockof-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A9, A11 (x4), A2-A9 (x8) or A2-A8 (x16) select the blockof-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A9, A11 (x4), A3-A9 (x8) or A3-A8 (x16) select the blockof-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) select the unique column to be accessed, and mode register bit M3 is ignored.
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SDRAM AC CHARACTERISTICS
Parameter Clock Cycle Time (1) CL = 3 CL = 2 Symbol tCC tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD 133MHz Min 7 7.5 3 2.5 3 2 1 1.0 7 15 15 20 50 60 70 1 1 1 1.5 2 1 20 20 20 50 70 70 1 1 1 1.5 2 2 Max 1000 1000 5.4 125MHz Min 8 10 3 3 3 2 1 1.0 7 20 20 24 60 80 80 1 1 1 1.5 2 1 Max 1000 1000 6
WED3DL328V
100MHz Min 10 12 3 3 3 2 1 1.0 8 Max 1000 1000 7
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CK CK CK CK ea
Clock to valid Output delay (1,2) Output Data Hold Time (2) Clock HIGH Pulse Width (3) Clock LOW Pulse Width (3) Input Setup Time (3) Input Hold Time (3) CK to Output Low-Z (2) CK to Output High-Z Row Active to Row Active Delay (4) RAS# to CAS# Delay (4) Row Precharge Time (4) Row Active Time (4) Row Cycle Time - Operation (4) Row Cycle Time - Auto Refresh (4,8) Last Data in to New Column Address Delay (5) Last Data in to Row Precharge (5) Last Data in to Burst Stop (5) Column Address to Column Address Delay (6) Number of Valid OutputData (7)
120,000
120,000
120,000
NOTES: 1. Parameters depend on programmed CAS# latency. 2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given trfc after self-refresh exit.
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COMMAND TRUTH TABLE
CKE Function Mode Register Set Auto Refresh (CBR) Refresh Entry Self Refresh Single Bank Precharge Precharge Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto Precharge Burst Termination No Operation Device Deselect Clock Suspend/Standby Mode Data Write/Output Disable Data Mask/Output Disable Entry Power Down Mode Exit Register Previous Current Cycle Cycle H X H H H L H X H X H X H X H X H X H X H X H X H X L X H X H X X L X H CE# L L L L L L L L L L L L H X X X H H RAS# L L L L L L H H H H H H X X X X X X CAS# L L L H H H L L L L H H X X X X X X WE# L H H L L H L L L H L H X X X X X X DQM X X X X X X X X X X X X X X L H X X BA
WED3DL328V
A10/AP A9-0
A11
Notes
X X BA X BA BA BA BA BA X X X X X X X X
OP CODE X X X X L X H X Row Address L Column H Column L Column H Column X X X X X X X X X X X X X X X X
2 2 2 2 2 2 3
4 5 5 6 6
Notes: 1. All of the SDRAM operations are defined by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock. 2. Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS# latency. 4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations, therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
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CLOCK ENABLE (CKE) TRUTH TABLE
CKE Current State Previous Cycle H L L L L L L H L L H H H H H H H H H H H L H Any State other than listed above H L L Current Cycle X H H H H H L X H H X H H H H H L L L L H X H L H L CE# X H L L L L X X H L L H L L L L H L L L L X X X X X RAS# X X H H H L X X X X H X H L L L X H L L L X X X X X Command CAS# X X H H L X X X X X L X X H L L X X H L L X X X X X WE# X X H L X X X X X X L X X X H L X X X H L X X X X X BA0-1 X X X X X X X X X X X A10-11 X X X X X X X X X X
WED3DL328V
Action INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down Mode exit, all banks idle ILLEGAL Maintain Power Down Mode Refer to the Idle State section of the Current State Truth Table
Notes 1 2 2 2 2 2 1 2 2 2 3
Self Refresh
Power Down
X X OP Code
CBR Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table
4 3 4 4
All Banks Idle
X X OP Code X X X X X X X X X X
Entry Self Refresh Mode Register Set Power Down Refer to the Operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
5
NOTES: 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before any command other than Exit is issued. 3. The address inputs (A11-0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. Must be a legal command as defined in the Current State Truth Table.
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CURRENT STATE TRUTH TABLE
Command Current State CE# L L L L Idle L L L L H L L L L Row Active L L L L H L L L L Read L L L L H L L L L Write L L L L H L L L Read with Auto Precharge L L L L L H
June, 2002 Rev. 1
WED3DL328V
RAS# L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X
CAS# L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X
WE# L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X
BA0-1 X X BA BA BA X X X
A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X
9
Description Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
Action Set the Mode Register Start Auto orSelf Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst
Notes 2 2,3
4 2 2 5
X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X
6 2 7,8 7,8
4 8,9 8,9
4 8,9 8,9
4 4
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CURRENT STATE TRUTH TABLE (CONT.)
Command Current State CE# L L L Write with Auto Precharge L L L L L H L L L L Precharging L L L L H L L L L Row Activating L L L L H L L L L Write Recovering L L L L H L L L Write Recovering with Auto Precharge L L L L L H
June, 2002 Rev. 1
WED3DL328V
RAS# L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X
CAS# L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X
WE# L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X
BA0-1 X X BA BA BA X X X
A11, A10/AP-A0 OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X
Description Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect
Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL
Notes
4 4
X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X
4 4 4
4 4,10 4 4
4 4 9 9
4 4 4,9 4,9
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CURRENT STATE TRUTH TABLE (CONT.)
Command Current State CE# L L L L Refreshing L L L L H L L L Mode Register Accessing L L L L L H RAS# L L L L H H H H X L L L L H H H H X CAS# L L H H L L H H X L L H H L L H H X WE# L H L H L H L H X L H L H L H L H X X X BA BA BA X X X X X BA BA BA X X X OP Code X X Row Address Column Column X X X BA0-1 A11, A10/AP-A0 OP Code X X Row Address Column Column X X X Description Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Action
WED3DL328V
Notes
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles
NOTES: 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. Both Banks must be idle otherwise it is an illegal action. 3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered. 4. The Current State only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current Sate then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS# to CAS# Delay (tRCD) must occur before the command is given. 8. Address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not satified.
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WED3DL328V
FIG. 3 SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS LATENCY=3, BURST LENGTH=1
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t CC
CKE
t CH
t CL
HIGH
t RAS
CE#
t RCD
t SS
RAS#
t SH
t RCD
t SS
t SH
t RP
t SS
CAS#
t SH
t CCD
t SS
ADDR
t SH
Ra Ca
t SS
Cb
t SH
Cc
Rb
Note 2
Note 2, 3
Note 2, 3
Note 2, 3 Note 4
Note 2
BA
BS
BS
BS
BS
BS
BS
A10/AP
Ra
Note 3
Note 3
Note 3
Note 4
Rb
t RAC
t SAC
DQ
t SS
Qa
Db
t SH
Qc
t SLZ
WE#
t OH
t SS
t SH
t SS
DQM
t SH
Row Active
Read
Write
Read
Precharge
Row Active
DON'T CARE
NOTES: 1. All input except CKE & DQM can be don't care when CE# is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA0~BA1.
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP BA0 BA1 0 0 0 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 Operation Distribute auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Disable auto precharge, leave bank C active at end of burst. Disable auto precharge, leave bank D active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst. Enable auto precharge, precharge bank C at end of burst. Enable auto precharge, precharge bank D at end of burst.
BA0 0 0 1 1
BA1 0 1 0 1
Active & Read/Write Bank A Bank B Bank C Bank D
4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted.
A10/AP 0 0 0 0 1
June, 2002 Rev. 1
BA0 0 0 1 1 x
BA1 0 1 0 1 x
Precharge Bank A Bank B Bank C Bank D All Banks
White Electronic Designs Corp. reserves the right to change products or specifications without notice. 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 4 POWER UP SEQUENCE
0
CLOCK
WED3DL328V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
High level is necessary
CE#
t RP
RAS#
t RFC
t RFC
CAS#
ADDR
Key
RAa
BA
A10/AP
RAa
DQ
HIGH-Z
WE#
DQM
High level is necessary
Precharge (All Banks)
Auto Refresh
Auto Refresh
Mode Register Set
Row Active (A-Bank)
DON'T CARE
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 13 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 5 READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
0
CLOCK
WED3DL328V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
HIGH
t RC
CE#
Note 1
t RCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
Rb
Note 3
t RAC
t SAC
Qa0
t OH
Qa1
t SHZ Note 4
Qa2
t RDL
Db0
CL = 2 DQ
Qa3
Db1
Db2
Db3
t RAC
Note 3
t SAC
Qa0
t OH
Qa1
t SHZ
Qa2
Note 4
t RDL
Db0
CL = 3
Qa3
Db1
Db2
Db3
WE#
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS# Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS# latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst (1, 2, 4, 8 & full page bit burst).
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 14 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 6 PAGE READ & WRITE CYCLE AT SAME BANK @BURST LENGTH=4
0
CLOCK
WED3DL328V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
HIGH
CE#
t RCD
RAS#
Note 2
CAS#
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
Ra
t RDL
CL = 2 DQ
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
t CDL
CL = 3
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
WE#
Note 1
Note 3
DQM
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 15 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 7 PAGE READ CYCLE AT DIFFERENT BANK @BURST LENGTH=4
0
CLOCK
WED3DL328V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
Note 1
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
BA
A10/AP
RAa
RBb
CL = 2 DQ
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2 QBb3
QAc0
QAc1
QBd0
QBd1 QAe0
QAe1
CL = 3
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0 QBd1
QAe0
QAe1
WE#
DQM
Row Active (A-Bank)
Row Active (B-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
Read (A-Bank)
DON'T CARE
NOTES: 1. CE# can be don't cared when RAS#, CAS# and WE# are high at the clock high going edge. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 16 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 8 PAGE WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL328V
17
18
19
CLOCK
CKE
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
BA
A10/AP
RAa
RBb
t CDL
DQ
DAa0
t RDL
DBb1
DBb2
DBb3
DAc0
DAc1
DBd0
DBd1
DAa1
DAa2
DAa3
DBb0
WE#
Note 1
DQM
Row Active (A-Bank)
Row Active (B-Bank)
Write (A-Bank)
Write (B-Bank)
Write (A-Bank)
Write (B-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 17 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 9 READ & WRITE CYCLE AT DIFFERENT BANK @BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL328V
17
18
19
CLOCK
CKE
HIGH
CE#
RAS#
CAS#
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A10/AP
RAa
RBb
RAc
t CDL
CL = 2
DQ CL = 3
QAa0
Note 1
QAa0
QAa1
QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
QAc0
QAc1
QAc2
QAa1
QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
QAc0
QAc1
WE#
DQM
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (B-Bank)
Write (B-Bank)
Read (A-Bank)
DON'T CARE
Row Active (A-Bank)
NOTE: 1. tCDL should be met to complete write.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 18 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED3DL328V
FIG. 10 READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CE#
RAS#
CAS#
ADDR
Ra
Rb
Ca
Cb
BA
A10/AP
Ra
Rb
CL = 2
DQ CL = 3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
WE#
DQM
Row Active (A-Bank)
Read with Auto Precharge (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
DON'T CARE
NOTE: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (in the case of Burst Length=1 & 2 and BRSW mode)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 19 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED3DL328V
FIG. 11 CLOCK SUSPENSION & DQM OPERATION CYCLE @CAS LATENCY=2, BURST LENGTH=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CE#
RAS#
CAS#
ADDR
Ra
Ca
Cb
Cc
BA
A10/AP
Ra
t SHZ
DQ
Qa0
Qa1
Qa2
Qa3
Qb1
t SHZ
Qb1
Dc0
Dc2
WE#
Note 1
DQM
Row Active
Read
Clock Suspension
Read
Read DQM
Write
Write DQM
Clock Suspension
Write DQM
DON'T CARE
NOTE: 1. DQM is needed to prevent bus contention.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 20 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED3DL328V
FIG. 12 READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @BURST LENGTH=FULL PAGE
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
HIGH
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
Note 3
1
1
CL = 2
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
DQ
2 2
CL = 3
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
WE#
DQM
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is same as the case of RAS# interrupt. Both cases are illustrated in above timing diagram. See the label 1, 2. But at burst write, Burst stop and RAS# interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle." 3. Burst stop is valid at every burst length.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 21 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED3DL328V
FIG. 13 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @BURST LENGTH=FULL PAGE
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
HIGH
CE#
RAS#
CAS#
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
t BDL
DQ
t RDL
Note 2
DAa0
DAa1
DAa2
DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
WE#
DQM
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
DON'T CARE
NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 22 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 14 BURST READ SINGLE BIT WRITE CYCLE @BURST LENGTH=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WED3DL328V
17
18
19
CLOCK
Note 1
CKE
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A10/AP
RAa
RBb
RAc
CL = 2
DQ CL = 3
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
WE#
DQM
Row Active (A-Bank)
Row Active (B-Bank)
Write (A-Bank)
Read with Auto Precharge (A-Bank)
Row Active (A-Bank)
Write with Auto Precharge (B-Bank)
Read (A-Bank)
Precharge (Both Banks)
DON'T CARE
NOTES: 1. BRSW mode is enabled by setting As "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 23 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED3DL328V
FIG. 15 ACTIVE/PRECHARGE POWER DOWN MODE @CAS# LATENCY=2, BURST LENGTH=4
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t SS
CKE
Note 1
Note 3
Note 2
t SS
t SS
CE#
RAS#
CAS#
ADDR
Ra
Ca
BA
A10/AP
Ra
t SHZ
DQ
Qa0
Qa1
Qa2
WE#
DQM
Precharge Power-Down Entry
Row Active
Read
Precharge
DON'T CARE
Active Precharge Power-Down Power-Down Entry Exit
Active Power-Down Exit
NOTES: 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1 CK + tSS prior to Row active command. 3. Cannot violate minimum refresh specification (64ms).
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 24 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 16 SELF REFRESH ENTRY & EXIT CYCLE
0
CLOCK
WED3DL328V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t SS
CKE
Note 1
Note 2
Note 4
Note 3
t RFC min
Note 6
CE#
Note 5
RAS#
Note 7
CAS#
ADDR
BA
A10/AP
DQ
HI-Z
HI-Z
WE#
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
DON'T CARE
NOTES: TO ENTER SELF REFRESH MODE 1. CE#, RAS# & CAS# with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low." Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CE# starts from high. 6. Minimum tRFC is required after CKE going high to complete self refresh exit. 7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 25 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIG. 17 MODE REGISTER SET CYCLE
0
CLOCK
WED3DL328V
FIG. 18 AUTO REFRESH CYCLE
8 0 1 2 3 4 5 6 7 8 9 10
1
2
3
4
5
6
7
CKE
HIGH
HIGH
CE#
Note 2
t RFC
RAS#
Note 1
CAS#
Note 3
ADDR
Key
Ra
DQ
HI-Z
HI-Z
WE#
DQM
MRS
New Command
Auto Refresh
New Command
DON'T CARE
NOTES: Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE 1. CE#, RAS#, CAS#, & WE# activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS# activation. 3. Please refer to Mode Register Set table.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 26 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PACKAGE DESCRIPTION 119 PIN BGA JEDEC MO-163
7.62 (0.300) TYP
A B C D E F G
A1 CORNER
WED3DL328V
2.79 (0.110) MAX
R 1.52 (0.060) MAX (4x)
14.00 (0.551) TYP
1.27 (0.050) TYP
22.00 (0.866) TYP
20.32 (0.800) TYP
H J K L M N P R T U
1.27 (0.050) TYP
0.711 (0.028) MAX
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
Part Number WED3DL328V7BC WED3DL328V8BC WED3DL328V10BC WED3DL328V7BI WED3DL328V8BI WED3DL328V10BI Clock Frequency 133MHZ 125MHZ 100MHZ 133MHZ 125MHZ 100MHZ Package 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA Operating Range Commercial Commercial Commercial Industrial Industrial Industrial
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June, 2002 Rev. 1 27 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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